----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:10:21 02/25/2011 
-- Design Name: 
-- Module Name:    interfaz - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Definitions.ALL;
--use work.ram.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity interfaz is
    Port ( PC : in instr_addr_type;
			  clk_i : in  STD_LOGIC;
			  proc_state : in processor_state;
           instr_cyc_o : out  STD_LOGIC;
           instr_stb_o : out  STD_LOGIC;
           instr_ack_i : in  STD_LOGIC;
           instr_addr_o : out  instr_addr_type;
           instr_word_i : in  instr_word_type;
           data_cyc_o : out  STD_LOGIC;
           data_stb_o : out  STD_LOGIC;
           data_we_o : out  STD_LOGIC;
           data_ack_i : in  STD_LOGIC;
           data_addr_o : out  data_addr_type;
           data_word_o : out  data_word_type;
           data_word_i : in  data_word_type;
           port_cyc_o : out  STD_LOGIC;
           por_stb_o : out  STD_LOGIC;
           port_we_o : out  STD_LOGIC;
           port_ack_i : in  STD_LOGIC;
           port_addr_o : out  port_addr_type;
           port_word_o : out  port_word_type;
           port_word_i : in  port_word_type;
			  ir : out instr_word_type;
			  acc : in data_addr_type;
			  reg : in data_word_type;
			  pc_out : in instr_addr_type;
			  is_load : in STD_LOGIC;
			  is_store : in STD_LOGIC;
			  we_o : out STD_LOGIC;
           clr_i : in  STD_LOGIC);

end interfaz;

architecture Behavioral of interfaz is

begin
	process (clk_i,clr_i,proc_state,pc,instr_ack_i,instr_word_i)
	begin
		if(proc_state=execute or proc_state=mem) then
			data_cyc_o <= '1';
			data_stb_o <= '1';
			if (is_load='1') then
				data_we_o<='1';
				if(data_ack_i<='1') then
					data_word_o<=memdata[acc];
				end if;
			end if;
			if (is_store='1') then
				data_we_o<='0';
				if(data_ack_i='1') then
					memdata[acc]<=data_word_i;
				end if;
			end if;
			port_cyc_o <= '0';
			port_stb_o <= '0';
			data_ack_i <= '0';
		end if;			
	end process;
end Behavioral;
